1. Field of the Invention
Generally, the present invention relates to the formation of integrated circuits, and, more particularly, to the formation of metallization layers including highly conductive metals, such as copper, embedded into a dielectric material having low permittivity to enhance device performance.
2. Description of the Related Art
In modern integrated circuits, minimum feature sizes, such as the channel length of field effect transistors, have reached the deep sub-micron range, thereby steadily increasing performance of these circuits in terms of speed and power consumption. As the size of the individual circuit elements is significantly reduced, thereby improving, for example, the switching speed of the transistor elements, the available floor space for interconnect lines electrically connecting the individual circuit elements is also decreased. Consequently, the dimensions of these interconnect lines have to be reduced to compensate for a reduced amount of available floor space and for an increased number of circuit elements provided per chip. In integrated circuits having minimum dimensions of approximately 0.35 μm and less, a limiting factor of device performance is the signal propagation delay caused by the switching speed of the transistor elements. As the channel length of these transistor elements has now reached 0.18 μm and less, it turns out, however, that the signal propagation delay is no longer limited by the field effect transistors, but is limited, owing to the increased circuit density, by the close proximity of the interconnect lines, since the line-to-line capacitance is increased in combination with a reduced conductivity of the lines due to their reduced cross-sectional area. The parasitic RC time constants, therefore, require the introduction of a new type of materials for forming the metallization layer.
Traditionally, metallization layers are formed by a dielectric layer stack including, for example, silicon dioxide and/or silicon nitride with aluminum as the typical metal. Since aluminum exhibits significant electromigration at higher current densities than may be necessary in integrated circuits having extremely scaled feature sizes, aluminum is being replaced by copper, which has a significantly lower electrical resistance and a higher resistivity against electromigration. For devices having feature sizes of 0.13 μm and less, it turns out that simply replacing aluminum with copper does not provide the required decrease of the parasitic RC time constants, and, therefore, the well-established and well-known dielectric materials, silicon dioxide (k approximately 4.2) and silicon nitride (k>5), are increasingly replaced by so-called low-k dielectric materials. However, the transition from the well-known and well-established aluminum/silicon dioxide metallization layer to a low-k dielectric/copper metallization layer is associated with a plurality of issues to be dealt with.
For example, copper may not be deposited in higher amounts in an efficient manner by well-established deposition methods, such as chemical and physical vapor deposition. Moreover, copper may not be efficiently patterned by well-established anisotropic etch processes; therefore, the so-called damascene technique is employed in forming metallization layers including copper lines. Typically, in the damascene technique, the dielectric layer is deposited and then patterned with trenches and vias that are subsequently filled with copper by plating methods, such as electroplating or electroless plating. Although the damascene technique is presently a well-established technique for forming copper metallization layers in standard dielectric materials, such as silicon dioxide, the employment of low-k dielectrics requires the development of new dielectric diffusion barrier layers so as to avoid copper contamination of adjacent material layers, as copper readily diffuses in a plurality of dielectrics. Although silicon nitride is known as an effective copper diffusion barrier, silicon nitride may not be considered appropriate in low-k dielectric layer stacks owing to its high permittivity. Therefore, silicon carbide is presently considered as a viable candidate for a copper diffusion barrier. It turns out, however, that copper's resistance against electromigration strongly depends on the interface between the copper and the adjacent diffusion barrier layer, and, therefore, in sophisticated integrated circuits featuring high current densities, it is generally preferable to use up to 20% nitrogen in the silicon carbide layer, thereby remarkably improving the electromigration behavior of copper compared to pure silicon carbide.
A further problem in forming low-k copper metallization layers has been under-estimated in the past and is now considered a major challenge in the integration of low-k dielectrics. During the patterning of the low-k dielectric material, standard photolithography is used to image the required structure into the deep UV photoresist. In developing the photoresist, certain portions of the resist which have been exposed may not be completely removed as required and thus the structure may not be correctly transferred into the underlying low-k dielectric material. The effect of insufficiently developing the photoresist is also referred to as resist poisoning. With reference to FIGS. 1a-1e, a typical conventional process flow will now be described to explain the problems involved in forming a metallization layer including copper and a low-k dielectric in more detail.
FIG. 1a schematically shows a cross-sectional view of a semiconductor structure 100, in which a low-k dielectric material is to be patterned in accordance with a so-called via first/trench last process sequence, which is presently considered the most promising process scheme in patterning low-k dielectrics. The semiconductor structure 100 comprises a substrate 101 that may include circuit elements, such as transistors, resistors, capacitors and the like, and which may include a lower metallization layer 102 including a metal region 103 embedded in a dielectric material 104. Depending on the level of the lower metallization layer 102, the metal region 103 may comprise copper and the dielectric 104 may be a low-k dielectric, such as hydrogen-containing silicon oxycarbide (SiCOH). A barrier layer 105 is formed of nitrogen containing silicon carbide (SiCN) which also serves as an etch stop layer in the following etch procedure for patterning an overlying low-k dielectric layer 106. The low-k dielectric layer 106 may comprise, depending on the process sequence used, an intermediate silicon carbide etch stop layer 107, which in many applications may, however, be omitted for the benefit of a reduced total permittivity. The low-k dielectric material in the layer 106 may comprise SiCOH. A cap layer 108, for example comprised of oxide or provided as an anti-reflective coating (ARC), may optionally be located on the low-k dielectric layer 106 and may then serve as a stop layer in removing excess copper in a subsequent chemical mechanical polishing (CMP) process. A resist mask 109 including an opening 110 is formed above the optional cap layer 108.
A typical process flow for forming the semiconductor structure 100, as shown in FIG. 1a, may comprise the following steps. After planarizing the lower metallization layer 102, the barrier/etch stop layer 105 is deposited by, for example, a plasma enhanced chemical vapor deposition (PECVD) from trimethyl silane (3MS) and ammonia (NH3) as precursor gases. Then, the hydrogen-containing silicon oxycarbide is deposited, wherein, if required, the silicon carbide layer 107 is formed when a first required thickness of the dielectric layer 106 is obtained. Thereafter, the residual layer 106 is deposited to achieve the required overall thickness of the layer 106. Next, the cap layer 108, if required, is deposited with a required thickness. The cap layer 108 may help to substantially avoid any interaction of the low-k dielectric of the layer 106 with the overlying resist mask 109 and may serve as a CMP stop layer. Then the resist mask 109 is patterned in accordance with well-established deep UV lithography techniques to form the opening 110 determining the dimensions of the vias to be formed within the dielectric layer 106.
FIG. 1b schematically shows the semiconductor structure 100 after an anisotropic etch process for forming a via 111 in the cap layer 108 and the dielectric layer 106. During the anisotropic etch procedure, the barrier/etch stop layer 105 exhibits a significantly lower etch rate than the surrounding dielectric layer 106, so that the etch process may be stopped in or on the layer 105. Thereafter, the remaining photoresist not consumed during the anisotropic etch process is removed by an etch step in an oxygen-containing plasma ambient. It should be noted that, in particular, the nitrogen contained in the barrier/etch stop layer 105 may readily diffuse into the low-k dielectric of the layer 106 due to the desired porosity of this material. Since the cap layer 108 substantially prevents any diffusion from nitrogen or nitrogen-containing compounds into the overlying resist mask 109, the patterning of the opening 110 and the subsequent patterning of the via 111 is substantially not affected by any resist poisoning effects.
FIG. 1c schematically shows the semiconductor structure 100 in an advanced manufacturing stage. The via 111 is filled with an organic anti-reflective coating material so as to include a via plug 114, whereas the organic material is provided at the remaining surface of the structure 100 so as to form an anti-reflective coating layer 112 for the subsequent photolithography. Thus, the plug 114 and the anti-reflective coating 112 serve to planarize the topography of the semiconductor structure 100 prior to the formation of a further photoresist mask 113. As shown, the photoresist mask 113 includes a trench opening 115 at the bottom of which resist residuals 116 are maintained.
The via plug 114 and the anti-reflective coating 112 may be formed by spin-on techniques and the like, and the photoresist mask 113 may be formed by sophisticated lithography methods, as are well known in the art. Contrary to the formation of the resist mask 109, nitrogen or nitrogen compounds may readily diffuse in the organic anti-reflective coating material and may now come into contact with the overlying photoresist 113, since the protecting cap layer 108 is open at the via 111. The interaction of nitrogen and compounds thereof with the photoresist may deteriorate the light sensitivity of the resist. Consequently, upon exposure and development of the photoresist 113 in forming the trench opening 115, the resist residuals 116 remain and significantly affect the following anisotropic etch step for forming a trench in the upper portion of the dielectric layer 106.
FIG. 1d schematically shows the semiconductor structure 100 after completion of the trench forming step. As is evident from FIG. 1d, the trench 117 that should have been formed in the dielectric layer 106 is substantially not transferred from the photoresist mask 113 to the underlying cap layer 108 and the upper portion of the dielectric layer 106. Thus, after removing the remaining photoresist mask 113, the cap layer 108 and the dielectric layer 106 comprise substantially the via 111 without any trench in the upper portion of the layer 106. It should be noted that a so-called bi-layer is commonly used for the photoresist mask 113, wherein a lower portion of the bi-layer may comprise silicon so as to reduce the interaction of the photoresist with up-diffusing nitrogen and nitrogen compounds. It turns out, however, that even the provision of a photoresist bi-layer is insufficient in preventing resist poisoning. Moreover, even a significant increase of the thickness of the anti-reflective coating 112 may not efficiently prevent the overlying photoresist layer 113 from interacting with up-diffusing nitrogen-containing compounds.
FIG. 1e schematically shows the semiconductor structure 100 after completion of the metallization layer 130, including a barrier metal layer 118 on inner sidewalls and the bottom of the via 111, which is filled with copper 119. Moreover, a surface 120 of the metallization layer 130 is planarized to allow the formation of a further metallization layer.
Typically, the barrier metal layer 118 may be deposited by physical vapor deposition, such as sputter deposition, with a thickness that insures sufficient protection against copper out-diffusion and at the same time provides a required adhesion to the surrounding low-k dielectric material. Typically, tantalum or tantalum nitride may be used as the material for the barrier metal layer 118. Subsequently, a copper seed layer is deposited to promote the subsequent deposition of the bulk copper by electroplating. Then, the excess copper is removed by chemical mechanical polishing, wherein the cap layer 108 is also removed and acts as a stop layer to reliably control the CMP process. However, since the trenches 117 required for the electrical connection are missing, as shown in FIGS. 1d and 1e, or are at least substantially reduced in size, device failures consequently occur or at least a significantly reduced device reliability is obtained. Moreover, since electromigration of copper strongly depends on the characteristics of the interface to the surrounding material, it is important to maintain a required nitrogen concentration within the layer 105, especially at regions 121, in which the copper of the metal region 103 is in contact with the barrier/etch stop layer 105, so as to obtain the required electromigration behavior, an improved adhesion, and the like, compared to pure silicon carbide layers.
In view of the above problems, it is thus highly desirable to provide a technique that allows maintaining superior barrier characteristics without unduly promoting resist poisoning in the formation of low-k metallization layers.